The invention relates to a circuit arrangement for controlling a pulse output stage.
Output stages supply voltage pulses with a low internal resistance and make it possible, for example, to supply power to loads which are to be operated in a pulsed manner. Such loads may be, inter alia, pulsed diode lasers. Pulsed currents up to 100 A with pulse widths of a few ten nanoseconds are typically required here for diodes in the power range of a few ten watts peak power. Thyristors or MOS field-effect power transistors (MOS-FET) are frequently employed for such output stages, said MOS field-effect power transistors superseding the thyristors to an ever greater extent as a result of their low turn-on resistance.
A circuit arrangement for controlling a pulse output stage is disclosed in "Halbleiter Schaltungstechnik" Semiconductor Circuitry!, Springer-Verlag, 9 th edition, page 581 and, for the purpose of elucidation, is illustrated here in FIG. 3, using the example of an output stage controller of a diode laser. A MOS-FET 1 directly connects a diode laser (2) as the load to a capacitor (4), which has previously been charged to a suitably high voltage by a charging circuit (LS) 3, which is not explained in any detail. As a result, the capacitor (4) is discharged by a current pulse via the diode (2) and the MOS-FET (1), the voltage drops across the involved components and leads being divided depending on their impedance. A powerful controller (5), which supplies the large peak currents lying in the ampere range, is usually used. The disadvantage of this is that this controller both requires a dedicated voltage supply (SV) 6, which causes additional costs, and has its own power consumption, which is disadvantageous particularly in the case of small and light, portable devices, in particular also in the case of a low battery voltage. The dedicated voltage supply (6) of the controller is present because the permissible gate control voltage of commercially available MOS-FETs is at most 20 V, and then in output stages of this type is, as a rule, only a fraction of the voltage available at the charging circuit.
DE 33 01 648 A1 describes a power stage in which an input amplifier is connected upstream of the gate of a power FET. The control signal is applied to the input amplifier. The input amplifier comprises two FETs connected in parallel. The drain voltage of the power FET is present at the drain of one of the amplifier FETs. The gate of the power FET is connected to the source terminals of the amplifier FETs. The output voltage generated at the latter follows solely the control signal, and not the drain voltage. Since the drain and gate of the power FET are not connected directly via the control circuit, the gate is actively protected against a possibly excessively high drain voltage.